27 Aug 2019 Process development for flux-free soldering with preforms (Part 1)
Compared to standard reflow soldering with paste, the process development for paste-free soldering is much more elaborate. It is crucial to consider the quality requirements of the product from the very beginning. A preform is defined as a rolled metal sheet that consists solely of the solder alloy. This article discusses the most common requirements and presents, step-by-step, the systematic process development of flux-free soldering.
The first part deals with the quality requirements for the soldering process and the products.
Content of this post
The individual steps for the development of a flux-free solder profile with formic acid are shown. These include:
- Quality requirements
- Solder alloy
- Reduction agent operating temperature
- Temperature measurement: measurement dummy and data logger
- Soldering profile and fixture development
- Wetting tests
- Soldering tests
- Process window
- Process control and big data
For the development of a flux-free soldering process, it is necessary to understand from where these high demands on the product’s quality derive. The most frequent specifications for power modules, along with ways to comply with these specifications, are described below. Table 1 shows the most common requirements for the die-attach interconnect (chip to substrate).
Table 1: Most frequent requirements for die-attach interconnects
|Requirement||Influence on||Solution by||Proof by|
|Void area cumulated / chip area||Thermal resistance, lifetime||Material quality, contamination, temperature profile, temperature distribution, atmospheres, solder fixtures, vacuum, warpage||X-Ray, C-SAM|
|Single void / chip area||lifetime, thermal behavior (hotspots)||Material quality, contamination, temperature profile, temperature distribution, atmospheres, solder fixtures, vacuum, warpage||X-Ray, C-SAM|
|Bond line thickness BLT||Lifetime increases with increasing thickness of bond lines, but thermal resistance increases as well||Soldering jigs, preforms with spacers||C-SAM, cross sectioning, CT, laserprofilometry|
|Chip tilt||lifetime, thermal resistance, wire bonding ability, inhomogeneous thermo-mechanical stress||Soldering jigs, preforms with spacers, preform quality||C-SAM, cross sectioning, laserprofilometry, 3D-microscopy|
|Die movement, positioning issues||Wire bonding ability, short circuits, influence on creep distance||Pick&place process (e.g. with bonding agent), soldering fixtures, vacuum settings, preform quality||Optical microscopy, automated optical inspection (AOI)|
|Chip warpage||Increase void rate, thermo-mechanical stress, altered electrical behavior||Chip metallization and manufacturing||Optical microscopy, automated optical inspection (AOI), laserprofilometry|
|Solder splashes||Short circuits, wire bonding ability, optical aspects||Warpage of dies, temperature profile, vacuum settings, material settings, solder alloy||Optical microscopy, automated optical inspection (AOI)|
|Tin dust||Molding, potting||Formic acid concentration and residence time, time and temperature above liquidus||Optical microscopy, automated optical inspection (AOI)|
|Substrate warpage||Wire bonding ability, stress on chips, influence on soldering to baseplates or thermal resistance to cooler||Layout, temperature profile, downholder systems, solder jigs, bondline thickness||Straight edge, optical or tactile measurement|
|Tolerances||Lead to decreased Power Cycling lifetime, respectively to increase in rejects as well as variations in reliability, thermal impedance Zth||Material, soldering jigs, manual processes||Manufacturer, statistics|
The void-rate (porosity) is the most common criteria for die-attach layers. The porosity is distinguished in either single voids or total void rate referring to the total interconnect area (chip area). Voids can have various root causes. Mostly, poor material quality of the join partners is the reason for increased void rates above 5 %. Voids are normally detected by x-ray analysis or c-sam. X-ray machines perform automated void-rate calculations based on the grey-scale or edge detection method. An accurate solder layer is essential to minimize the thermal resistance of the interconnect. Additionally, voids can act as fissures that cause material fatigue.
Another crucial aspect for the lifetime of the product is the bond line thickness. If the bond line is too thin, the thermo-mechanical stress within the layer will increase, which may result in early failures. The thickness is measured by cross sectioning. Spacers can ensure a minimum bondline thickness.
The same facts can be applied to chip tilting. Die or chip movement can have various causes; among them the pick&place process, the preform quality and the solder amount. A misaligned chip on the other hand may cause problems during the wire bonding process due to issues with image recognition. The usage of bonding agents can prevent die movement. The inspection is normally performed via automated optical inspection (AOI).
Die warpage normally occurs due to wrong chip metallization or bondline thickness. During the soldering process, the warpage can only be prevented by applying solder fixtures (pressure) and controlled heating and cooling gradients. Once again, the inspection is performed via AOI. Strong chip warpage may cause major voids. When these voids are abruptly removed by vacuum, splashing can occur. The splashing, in turn, can lead to short circuits. The best prevention is to solve the cause of this issue. Secondly, it is useful to improve the vacuum settings.
Tin dust is a result of an increased formic acid concentration or an increased soaking time of the acid. Tin salt occurs during the formic acid reaction. At higher temperatures the salt dissolves, condensates on the surface of the substrate and leaves behind a tin dust. Tin dust affects the product optically and can cause voids/delamination of the molding/potting compound.
Movement of semiconductors can occur due to various causes. These include the placement process, preform quality and solder quantity. A moved or shifted chip leads to issues in the subsequent bonding process due to recognition problems of the wire bonder. The use of tacking agents during placement can prevent the chip from shifting. Detection is usually performed by automatic optical inspection systems (AOI).
Substrate warpage highly depends on the layout of the interconnect device. It can be prevented by using downholder systems that push down the substrate to an even plate. Heating and cooling slopes are important as well.
System solder layers (DBC to coolant or baseplate) have the same requirements as chip solder. Table 2 shows an overview. An important aspect is the pre-bending of the baseplate. To achieve a sufficient thermal contact to the cooler, the baseplate must be flat after the soldering process. Relevant factors to ensure that the end result is as desired are the pre-bending angle, the downholders and the temperature ramps. The proof is done via optical inspection systems or tactile measurements.
Table 2: System solder requirements (supplementary to Table 1)
|Requirement||Influence on||Solution by||Proof by|
|Substrate tilting||Lifetime, inhomogeneous thermal resistance, wire bondability, inhomogeneous thermo-mechanic stress||Soldering jigs, preforms with spacers, preform quality||C-SAM, cross sectioning, Laserprofilometry, 3D-microscopy|
|Solder splashes||Short circuits, wire bondability, optical issues||Warpage of dies, temperature profile, vacuum settings, material quality, solder alloy||Optical microscopy, automated optical inspection (AOI)|
|Baseplate warpage||Increased thermal resistance to cooler, thermo-mechanical stress||Pre-bending, soldering profile, substrate layout, solder thickness||Straight edge, optical or tactile measurement|
|Substrate movement / positoning errors||Welding of load terminals, wire-bonding, optical issues||Soldering jigs, temperature profile, vacuum settings||Optical microscopy, automated optical inspection (AOI)|
Double-sided power modules pose big challenge for the soldering process. In order to take advantage of double-sided cooling, it is imperative that the modules exhibit a sufficient co-planarity which ensures a good thermal connection to the cooler. Due to the usage of multiple modules, the tolerance of the total thickness must not exceed the tolerances. The tolerances for the molding process are within (extremely) narrow limits. To fulfil all these requirements, customized soldering jigs and downholder systems are necessary, which must be developed and tested for the particular product. The module design (position and size of dies) is a crucial factor in this process, as the module design, the soldering process and the fixtures need to be aligned.
Table 3: Requirements on the soldering process for double-sided power modules
|Requirement||Influence on||Solution by|
|Co-planarity of the module||Molding process, increased thermal resistance||Soldering fixtures, layout, soldering profile|
|Deviation of the total module thickness (of double-sided modules)||Molding process, thermal resistance at the cooler||Material tolerances, soldering jigs|
- Process development for flux-free soldering with preforms (Part 2)
- Process development for flux-free soldering with preforms (Part 3)
- Process development for flux-free soldering with preforms (Part 4)
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